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having it occur 2 ns earlier than the reference clock. Now data, in order to be safely clocked into the second segment register, can experience a delay of 10 + 2 + 13 + 2, or 27ns. Using a 7ns clock that is referenced to t0 = 0, this is 1ns earlier than the fourth clock (4 ´ 7 - 1 = 27ns).
¨
Thus, constructive skewing of the clock, as illustrated previously, allows the fastest possible synchronous cycle times. As in any pipelined system, no useful results appear at the output until the pipeline is full.
Using Pmin delays and constructive clock skew (CS­) as shown in the preceding improves the cycle time by using the Pmin delay to act as a storage element. Extensive use of such techniques is still largely a research area. Wong [311] reports being able to attain a clock speedup of 2.5 by using these techniques. For most of this text, we assume a cycle time defined by Pmin without taking advantage of Pmin.
Notice that uncontrolled clock skew in a wave pipelined system can have an even greater effect on cycle time than in a conventionally clocked system. If the uncontrolled skew in the arrival of the clock is ±d, its effect on C can be
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C = td + tg + 4d.
2.3 Cost-Area
Much of this book is devoted to understanding issues of performance. Included in this is the analysis of various memory configurations and processor design choices. Determining performance is relatively straightforward. A basic measure of performance is the product of the cycle time, the number of cycles per instruction (the CPI), and the number of instructions that an architecture executes (particularly in relation to another architecture).
Determining the goodness of a processor design is much more difficult. A good design is not simply the fastest possible processor implementation. Implementation and performance must be balanced with cost. A good design achieves an optimum cost-performance tradeoff at a particular target performance.
Moreover, there are a host of other issues that are secondary to the design itself, but directly influence the program cost and hence the product cost. These same issues may influence the marketability of the product. Some of these issues include:
Compatibility.
Applicability to the marketplace.
Upgradability.
Design time.
Reliability.

 
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