The total time for execution through all S stages of the pipeline is called the latency:
EXAMPLE 2.1
Suppose we have the following three-segment pipeline:
with C = 2 ns.
Segment #1
Pmax1 = 10 ns
Pmin1 = 7 ns
Segment #2
Pmax2 = 13 ns
Pmin2 = 8 ns
Segment #3
Pmax3 = 12 ns
Pmin3 = 9 ns
The respective segment cycle times are:
Dt1
=
10 - 7 + 2 = 5
Dt2
=
7
Dt3
=
5
max (Dti)
=
7.
The clock should be skewed (with respect to t = 0 inputs):
CS1
=
(10 + 2) mod 7 = 12 mod 7 = 5
CS2
=
(12 + 13 + 2) mod 7 = 27 mod 7 = 6 (or - 1 ns)
CS3
=
(27 + 12 + 2) mod 7 = 41 mod 7 = 6 (or - 1 ns).
The data from the first segment of the pipeline is not latched into the second stage until 12 ns after its entry into the first stage. If we designate the beginning of clock activation at the entry to segment #1 as t0 = 0, then this is the time when data begins to flow in the first segment. At 12 ns later the clock should be in a similar position with respect to the entry of the second pipeline segment. Even though the rate is 7 ns, the occurrence of the clock must be purposely skewed so that the data occurring on the maximum delay path is safely clocked into the storage element at the end of the first segment. Thus, the clock must be skewed by 5 ns (5 + 7 = 12). Skewing a 7 ns clock by 5 ns (i.e., delaying it by 5 ns) is exactly the same as
