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Page 788 transaction effects, 287 transaction processing, 288 transfer time, 608 unoverlapped, 644 translate, 65 translation lookaside buffer, 45, 323 transparent clock, 67 trap, 37 triple modular redundant processors, 512 true inclusion, 307 two-level cache, 293, 302 types of processors, 186 pipelined, 189 U uncontrolled clock skew, 69 underflow, 129 unified cache, 293 unity data traffic, 126 UNPACK, 165 unpacked decimal format, 17 update protocols, 541 user program level, 39 user state, 150 utilization, 367 V VAX, 1 vector accumulate, 433 vector facilities, 183 vector functional units, 428 vector instructions, 432 vector length, 454 vector memory, 437-452 vector operations, 433 compress, 434 expand, 434 vector processor, 427-437 vectorizable code, 453 vertical microinstruction, 8 very long instruction word, 426 virtual caches, 327 virtual effective address, 45 virtual to real mapping, 45 virtual to real translation, 322 VLIW, 426 W wafer, 85 wafer defects, 88 waiting time, 384 warm cache, 290 wave pipelining, 79, 135 well-mapped machines, 48, 49 windowed register sets, 126 working set, 39, 44 wraparound load, 284 write assembly cache, 293, 309 write-invalidate protocol, 541, 755 WTWA, 282 Y yield, 86
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