< previous page page_783 next page >

Page 783
d87111c01013bcda00bb8640fdff6754.gif
CBNWA, 282
d87111c01013bcda00bb8640fdff6754.gif
CFA, 113
d87111c01013bcda00bb8640fdff6754.gif
chaining, 436
d87111c01013bcda00bb8640fdff6754.gif
channel, 603-604
d87111c01013bcda00bb8640fdff6754.gif
character data type, 17
d87111c01013bcda00bb8640fdff6754.gif
character operand length, 170
d87111c01013bcda00bb8640fdff6754.gif
Chebyshev's inequality, 217
d87111c01013bcda00bb8640fdff6754.gif
chip floor planning, 94
d87111c01013bcda00bb8640fdff6754.gif
clock hazard, 68
d87111c01013bcda00bb8640fdff6754.gif
clock overhead, 66, 71
d87111c01013bcda00bb8640fdff6754.gif
clock pulse width, 68
d87111c01013bcda00bb8640fdff6754.gif
clock skew, 65
d87111c01013bcda00bb8640fdff6754.gif
closed queue, 374
d87111c01013bcda00bb8640fdff6754.gif
closed-queue model, 378
d87111c01013bcda00bb8640fdff6754.gif
clustering, 521
d87111c01013bcda00bb8640fdff6754.gif
code density, 118-119, 297-308
d87111c01013bcda00bb8640fdff6754.gif
coefficient of service time variance, 371
d87111c01013bcda00bb8640fdff6754.gif
coherency, 523-526
d87111c01013bcda00bb8640fdff6754.gif
cold caches, 290
d87111c01013bcda00bb8640fdff6754.gif
cold-start caches, 339
d87111c01013bcda00bb8640fdff6754.gif
color bits, 328-331
d87111c01013bcda00bb8640fdff6754.gif
colored pages, 328-331
d87111c01013bcda00bb8640fdff6754.gif
command, 3
d87111c01013bcda00bb8640fdff6754.gif
completion signal, 65
d87111c01013bcda00bb8640fdff6754.gif
compress, 434
d87111c01013bcda00bb8640fdff6754.gif
computer architecture, 1
d87111c01013bcda00bb8640fdff6754.gif
computer family analysis, 113
d87111c01013bcda00bb8640fdff6754.gif
concurrent processors, 425
d87111c01013bcda00bb8640fdff6754.gif
condition code, 31
d87111c01013bcda00bb8640fdff6754.gif
condition code testing, 163
d87111c01013bcda00bb8640fdff6754.gif
content address memory, 301
d87111c01013bcda00bb8640fdff6754.gif
contention time, 400
d87111c01013bcda00bb8640fdff6754.gif
context switch, 154
d87111c01013bcda00bb8640fdff6754.gif
contour buffer, 126
d87111c01013bcda00bb8640fdff6754.gif
control flow scheduling, 463, 467
d87111c01013bcda00bb8640fdff6754.gif
control point, 6
d87111c01013bcda00bb8640fdff6754.gif
control points, 7
d87111c01013bcda00bb8640fdff6754.gif
cost of multiple instructions, 482
d87111c01013bcda00bb8640fdff6754.gif
CPI, 109
d87111c01013bcda00bb8640fdff6754.gif
CPU time per instruction, 318
d87111c01013bcda00bb8640fdff6754.gif
Cragon's analysis, 139
d87111c01013bcda00bb8640fdff6754.gif
CSP language, 515
d87111c01013bcda00bb8640fdff6754.gif
CTPI, 318
d87111c01013bcda00bb8640fdff6754.gif
cycle, 3, 64-83
d87111c01013bcda00bb8640fdff6754.gif
cycle partitioning, 78
d87111c01013bcda00bb8640fdff6754.gif
cycle quantization, 77
d87111c01013bcda00bb8640fdff6754.gif
cycle time, 64-83, 612
d87111c01013bcda00bb8640fdff6754.gif
cycles per instruction, 109
d87111c01013bcda00bb8640fdff6754.gif
cylinder, 606
D
d87111c01013bcda00bb8640fdff6754.gif
data buffers, 124
d87111c01013bcda00bb8640fdff6754.gif
data dependency, 459, 462
d87111c01013bcda00bb8640fdff6754.gif
data fetch, 48, 66
d87111c01013bcda00bb8640fdff6754.gif
data flow scheduling, 467
d87111c01013bcda00bb8640fdff6754.gif
data interlocks, 214
d87111c01013bcda00bb8640fdff6754.gif
data paths, 4, 188
d87111c01013bcda00bb8640fdff6754.gif
data traffic expected per instruction, 314-321
d87111c01013bcda00bb8640fdff6754.gif
DEC Alpha, 101
d87111c01013bcda00bb8640fdff6754.gif
decimal arithmetic instructions, 171
d87111c01013bcda00bb8640fdff6754.gif
decimal data type, 16
d87111c01013bcda00bb8640fdff6754.gif
decimal operand length, 170
d87111c01013bcda00bb8640fdff6754.gif
decode, 65
d87111c01013bcda00bb8640fdff6754.gif
deep pipeline, 186
d87111c01013bcda00bb8640fdff6754.gif
defect, 85
d87111c01013bcda00bb8640fdff6754.gif
degree of interleaving, 359
d87111c01013bcda00bb8640fdff6754.gif
delay, 194
d87111c01013bcda00bb8640fdff6754.gif
delay slots, 211
d87111c01013bcda00bb8640fdff6754.gif
d-binomial model, 381
d87111c01013bcda00bb8640fdff6754.gif
demand fetch, 269
d87111c01013bcda00bb8640fdff6754.gif
design target miss rate, 274, 719-741
d87111c01013bcda00bb8640fdff6754.gif
die, 85
d87111c01013bcda00bb8640fdff6754.gif
direct mapping, 271
d87111c01013bcda00bb8640fdff6754.gif
directory hit, 269
d87111c01013bcda00bb8640fdff6754.gif
dirty line, 284
d87111c01013bcda00bb8640fdff6754.gif
disk access time, 608
d87111c01013bcda00bb8640fdff6754.gif
disk latency time, 618
d87111c01013bcda00bb8640fdff6754.gif
distributed disks, 639
d87111c01013bcda00bb8640fdff6754.gif
divide unit, 472
d87111c01013bcda00bb8640fdff6754.gif
Dragon protocol, 541, 755
d87111c01013bcda00bb8640fdff6754.gif
DRAM, 350, 747-749
d87111c01013bcda00bb8640fdff6754.gif
DTMR, 274, 719-741
d87111c01013bcda00bb8640fdff6754.gif
adjustments, 277
d87111c01013bcda00bb8640fdff6754.gif
dual-rank register, 66
d87111c01013bcda00bb8640fdff6754.gif
dynamic instruction count, 115, 141
d87111c01013bcda00bb8640fdff6754.gif
dynamic pipelined processor, 189
d87111c01013bcda00bb8640fdff6754.gif
dynamic pipelines, 189
d87111c01013bcda00bb8640fdff6754.gif
dynamic random access memory, 350-354
d87111c01013bcda00bb8640fdff6754.gif
dynamic strategy, 223
E
d87111c01013bcda00bb8640fdff6754.gif
ECC, 354-357
d87111c01013bcda00bb8640fdff6754.gif
economics of a processor, 103-109
d87111c01013bcda00bb8640fdff6754.gif
edge triggered, 67
d87111c01013bcda00bb8640fdff6754.gif
El Dorado, solid-state disks found in, 658
d87111c01013bcda00bb8640fdff6754.gif
error
d87111c01013bcda00bb8640fdff6754.gif
correction, 354
d87111c01013bcda00bb8640fdff6754.gif
detection, 354
d87111c01013bcda00bb8640fdff6754.gif
error correcting codes, 354-357
d87111c01013bcda00bb8640fdff6754.gif
essential dependency, 460

 
< previous page page_783 next page >