< previous page page_773 next page >

Page 773
d87111c01013bcda00bb8640fdff6754.gif
[152] G. Kane. MIPS R2000 RISC Architecture. Prentice-Hall, Englewood Cliffs, NJ, 1986.
d87111c01013bcda00bb8640fdff6754.gif
[153] G. Kane. MIPS RISC Architecture. Prentice-Hall, Englewood Cliffs, NJ, 1988.
d87111c01013bcda00bb8640fdff6754.gif
[154] G. Kane and J. Heinrich. MIPS RISC Architecture. Prentice-Hall, Englewood Cliffs, NJ, 1992.
d87111c01013bcda00bb8640fdff6754.gif
[155] A. H. Karp and H. P. Flatt. Measuring parallel processor performance. Communications of the ACM, 33(5):539543, May 1990.
d87111c01013bcda00bb8640fdff6754.gif
[156] M. Katevenis. Reduced Instruction Set Computer Architecture for VLSI. MIT Press, Cambridge, MA, 1985.
d87111c01013bcda00bb8640fdff6754.gif
[157] R. Katz, S. Eggers, D. Wood, C. Perkins, and R. Sheldon. Implementing a cache consistency protocol. In Proceedings of the 12th International Symposium on Computer Architecture, pages 276283. IEEE, 1985.
d87111c01013bcda00bb8640fdff6754.gif
[158] R. H. Katz, G. A. Gibson, and D. A. Patterson. Disk system architecture for high performance computing. Proceedings of the IEEE, 77(12):18421858, December 1989.
d87111c01013bcda00bb8640fdff6754.gif
[159] R. M, Keller. Look ahead processors. Computing Surveys, 7(4):177195, December 1975.
d87111c01013bcda00bb8640fdff6754.gif
[160] D. G. Kendall. Some problems in the theory of queues. Journal of the Royal Statistical Society, 13(2):151185, 1951.
d87111c01013bcda00bb8640fdff6754.gif
[161] T. Kilburn, D. B. G. Edwards, M. J. Lanigan, and F. H. Sumner. One-level storage system. IRE Transactions on Electronic Computers, EC-11(2):223235, April 1962.
d87111c01013bcda00bb8640fdff6754.gif
[162] M. Y. Kim. Synchronized disk interleaving. IEEE Transactions on Computers, C-35(11):978988, November 1986.
d87111c01013bcda00bb8640fdff6754.gif
[163] M. Y. Kim. Synchronously Interleaved Disk Systems. PhD thesis, Polytechnic Institute of New York, 1987.
d87111c01013bcda00bb8640fdff6754.gif
[164] E. F. Klass. Pushing the Limits of CMOS Technology by Using Wave Pipelining. PhD thesis, Delft University of Technology, September 1994.
d87111c01013bcda00bb8640fdff6754.gif
[165] F. Klass and J. M. Mulder. Use of cmos technology in wave pipelining. In Proceedings of the Fifth International Conference on VLSI Design, pages 303308, Bangalore, India, January 1992.
d87111c01013bcda00bb8640fdff6754.gif
[166] L. Kleinrock. Queueing Systems. Wiley, 1975. Two volumes.
d87111c01013bcda00bb8640fdff6754.gif
[167] D. Knuth. An empirical study of Fortran programs. Technical Report STANCS-70-186, Stanford University, 1970.
d87111c01013bcda00bb8640fdff6754.gif
[168] F. Kobayashi, Y. Watanabe, M. Yamamoto, A. Anzai, A. Takahashi, T. Daikoku, and T. Fujita. Hardware technology for Hitachi M-880 processor group. In Proceedings of the Electronic Components and Technologies Conference, pages 693703, 1991.
d87111c01013bcda00bb8640fdff6754.gif
[169] H. Kobayashi. Modeling and Analysis: An Introduction to Systems Performance Evaluation Methodology. Addison-Wesley, Menlo Park, CA, 1978.
d87111c01013bcda00bb8640fdff6754.gif
[170] M. Kobayashi. Dynamic profile of instruction sequences for the IBM System/370. IEEE Transactions on Computers, C-32(9):859861, 1983.
d87111c01013bcda00bb8640fdff6754.gif
[171] P. M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill, New York, 1981.
d87111c01013bcda00bb8640fdff6754.gif
[172] C. Kruskal and M. Snir. The performance of multistage interconnection networks for multiprocessors. IEEE Transactions on Computers, C-32(12), December 1983.

 
< previous page page_773 next page >