|
|
 |
|
|
|
|
[73] D. Ditzel and R. McLellan. Register allocation for free: the C machine stack cache. In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 4856, New York, March 1982. ACM. |
|
|
|
|
|
|
|
|
[74] K. M. Dixit. New CPU benchmark suites from SPEC. SPEC Newsletter, 4(1), February 1992. |
|
|
|
|
|
|
|
|
[75] R. Dowsing. Introduction to concurrency using Occam. Van Nostrand Reinhold, London, 1988. |
|
|
|
|
|
|
|
|
[76] P. K. Dubey and M. J. Flynn. A bubble propagation model for pipeline performance. Journal of Parallel and Distributed Computing, 23(3):330337, December 1994. |
|
|
|
|
|
|
|
|
[77] P. K. Dubey and M. J. Flynn. Optimal pipelining. Journal of Parallel and Distributed Computing, 8:1019, 1990. |
|
|
|
|
|
|
|
|
[78] Pradeep K. Dubey. Exploiting Fine-Grain Concurrency: Analytical Insights in Superscalar Processor Design. PhD thesis, Purdue University, August 1991. |
|
|
|
|
|
|
|
|
[79] M. Dubois, C. Scheurich, and F. Briggs. Memory access buffering in multiprocessors. In Proceedings of the 13th International Symposium on Computer Architecture, pages 434442, 1986. |
|
|
|
|
|
|
|
|
[80] M. Dubois, C. Scheurich, and F. Briggs. Synchronization, coherence and event ordering in multiprocessors. IEEE Computer, 21(2), 1988. |
|
|
|
|
|
|
|
|
[81] M. Dubois and S. Thakkar, editors. Scalable Shared-Memory Multiprocessors. Kluwer Academic, Boston, 1992. |
|
|
|
|
|
|
|
|
[82] M. C. Easton and R. Fagin. Cold-start vs. warm-start miss ratios. Communications of the ACM, 21(10):866872, October 1978. |
|
|
|
|
|
|
|
|
[83] S. Eggers. Simulation Analysis of Data Sharing in Shared Memory Multiprocessors. PhD thesis, University of California at Berkeley, 1989. Comp. Sci. Division Tech. Report UCB/CSD 89/501. |
|
|
|
|
|
|
|
|
[84] S. Eggers and R. Katz. A characterization of sharing in parallel programs and its applicability to coherency protocol evaluation. Technical Report Report No. UCB/CSD 87/387, University of California at Berkeley, December 1987. |
|
|
|
|
|
|
|
|
[85] R. J. Eickemeyer and J. H. Patel. Performance evaluation of on-chip register and cache organizations. Proceedings of the 15th Annual International Symposium on Computer Architecture, pages 6472, May 1988. |
|
|
|
|
|
|
|
|
[86] P. H. Enslow, editor. Multiprocessors and Parallel Processing, Wiley, New York, 1974. |
|
|
|
|
|
|
|
|
[87] W. Feller. An Introduction to Probability Theory and Its Application, volume 1. Wiley, New York, 1968. |
|
|
|
|
|
|
|
|
[88] P. M. Fenwick. Some aspects of the dynamic behavior of hierarchical memories. IEEE Transactions on Computers, C-34(6):570573, June 1985. |
|
|
|
|
|
|
|
|
[89] J. A. Fisher. Very long instruction word architectures and the ELI-512. In Proceedings of the 10th Symposium on Computer Architecture, pages 140150. ACM, 1983. |
|
|
|
|
|
|
|
|
[90] I. Flores. Derivation of a waiting time factor for a multiple band memory. Journal of the ACM, 11:265282, July 1964. |
|
|
|
|
|
|
|
|
[91] M. J. Flynn. Trends and problems in computer organization. In Proceedings of IFIP Congress, pages 210. North-Holland, Amsterdam, 1974. |
|
|
|
|
|
|
|
|
[92] M. J. Flynn and L. W. Hoevel. Execution architecture: The DELtran experiment. IEEE Transactions on Computers, C-32(2):156175, February 1983. |
|
|
|
|
|