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Here we review recent advances in dynamic random access memory (DRAM) technology and summarize by both chip level and system level comparisons. Data abstracted from Przybylski [?]. |
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Throughout the past two decades, various trends in memory designs have become apparent. |
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DRAM size has quadrupled every 3 years. (60% growth per year.) |
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Little change in the interface design resulted in low bandwidth growth. |
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Row access time has decreased approximately 7% every year. |
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Column access has decreased approximately 25% every year. |
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Processor demand on memory has increased despite heavy use of cache. |
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Bandwidth per bit has declined 25% per year. |
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The above data lead to a critical problemthe need to increase the bandwidth per bit. With this need in mind, new architectures, whether evolutionary or revolutionary, have been designed to deal with the bandwidth problem. |
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D.1 Typical Performance Enhancements |
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Use of block transfers. Basically, once a row has been fetched into the sense amps, the entire row is available for column access. As a result, the sense amps can be used as a cache to hold an entire row of data. |
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Use of page mode (static column mode). |
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Use of newer packages provides better pin-out density and electrical properties. |
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Use of low voltage electrical interfaces. |
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Use of synchronized interface. |
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Use of new bus or ring interfaces. |
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