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Figure 10.18
Baseline cache management policy/traffic analysis for 0.75m. |
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A glance at the results tells us that the WTNWA implementation has the highest offered occupancy among the four implementations. Even at a size of 128 bytes, the offered traffic is three times more than the available bandwidth. We show the adverse effect this has on overall performance as we take bus saturation into account in the CPI analysis. These data rule out the use of a WTNWA cache, since the bus has become the limiting resource even without multiple processors on the bus. In a multiprocessor system, we select either the CBWA with large line size or the WTNWA implementation with a secondary cache. Figure 10.19 shows that traffic is higher for the multiprocessor implementation. In the multiprocessor implementation, it is even more important to have a secondary cache to reduce bus traffic. |
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As Figure 10.20 for WTNWA shows, as line size is increased, the traffic from both data and instruction read references is reduced, but the data write traffic remains constant. In this implementation, the CPU performance is bus saturated. |
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Figure 10.21 gives the traffic breakdown for the CBWA implementation. One can see that as line size increases, reducing the cache miss ratio, a significant reduction in all three streams of traffic occurs. At a line size of 128 bytes, the bus occupancy is kept below 0.5, and processor performance degradation due to the bus contention among the three reference streams should be small. |
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Figure 10.22 shows the traffic breakdown of the WAC case. In using the write assembly cache, the data write traffic is converted from word traffic to the more efficient line traffic. Data from chapter 5 show that the WAC can filter out 70% of the write traffic. The write traffic is reduced, but still dominates the overall reference traffic. |
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