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Figure 10.17
Percent CPI improvement of implementations with secondary cache
relative to implementations without secondary cache for 0.3m across
different line sizes. |
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sizes. However, we have not taken memory traffic into account, and secondary cache plays an important part in reducing memory traffic. |
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Traffic on the memory bus is critical to overall system performance. When the offered bandwidth exceeds the achieved bandwidth, the memory bus dictates the performance of the overall system. The effect of bus traffic on a multiprocessor system is even more severe. Four main implementations can be considered: |
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Write-Through No Write Allocate cache. |
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Copy Back Write Allocate cache. |
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Write-Through No Write Allocate cache with a Write Assembly cache. |
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WTNWA with the addition of a secondary cache. |
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Now 8 ns of bus time are available to each instruction, and the offered bus time has to be below that to avoid significant performance degradation. The data are presented in two ways. We first compare to the total offered occupancy for each implementation, and we then break down the traffic of each implementation into different reference streams to get a better idea of the types of traffic on the bus and how they change with increasing line size. |
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