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Figure 10.11
Percent CPI improvement of CBWA buffer management schemes
2 and 3 relative to scheme 1 for 0.75m. (Write Policy-
Configuration-Buffer management scheme.) |
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which scheme to use, the CPI versus line size of each scheme was calculated. Figures 10.11 and 10.12 detail the performance improvement of schemes 2 and 3 relative to buffer management scheme 1. |
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A decision needs to be made with regard to the width of the memory bus. We calculate the effect of increasing the memory bus for both CBWA and WTNWA, and the results are displayed in Figures 10.1310.15. |
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These figures exhibit an interesting point. The increase in bus width brings a large return in CPI reduction for the CBWA case but not for the WTNWA case. It is somewhat intuitive that increasing bus width reduces Tline but does nothing for Taccess. Since WTNWA traffic is dominated by the write traffic as the miss ratio is reduced, its performance is not enhanced by a reduction in Tline. |
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Another interesting question is why the improvement reaches a peak for the MP-CBWA case at line size = 16 and reduces after that. This is due to the small cache area for the multiprocessor implementation. CPI reaches a peak at smaller line sizes. |
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For CBWA implementation, it is worthwhile in all cases to implement a wider memory interface, since the performance benefit is greater than 5% for reasonable line sizes. |
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