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Page 671 Table 10.2 ALU operation costs. Operation Single Double Add 1 cycle 1 cycle Integer Multiply 2 cycles 3 cycles Divide 16 cycles 32 cycles Add 2 cycles 2 cycles Floating Multiply 3 cycles 4 cycles Divide 13 cycles 27 cycles - Conditional case There is a 1-cycle delay for in-line, a 2.5-cycle delay for target, two unused in-line instructions fetched for branch to target, and no unused target instructions fetched for continue in-line. These numbers are not affected by the condition dependency distance. This case assumes that the pending instructions are stalled on decode of a conditional branch and are continued if the in-line path is the correct one. This results in a delay of one cycle instead of the anticipated half-cycle delay, as with the majority of instructions. This is due to a half-cycle delay due to the half-cycle skew, as well as an additional half-cycle delay, which is hidden in the reduced-scale processor version, since the decode and register fetch phases are contained in the same clock cycle. Run-on Instructions These instructions consist primarily of multiplication and division instructionssince this machine is designed for engineering applications, commercial instructions (for example, those instructions operating on character and BCD data) are not included. For this machine, we use a base value for addition of one cycle for single and one cycle for double precision, for multiplication of two cycles for single and three cycles for double precision, and for division one cycle per two bits (single or double precision). Floating-point normalization is assumed to take one additional cycle over the integer time. The results of the preceding analysis are presented in Tables 10.3 and 10.4. Using the operation distributions from Chapter 3, we can generate an estimated pipeline and branch delay penalties. 10.1.4 Pipeline Penalty Analysis In order to determine the expected penalties from the pipelines, we need to take the data from Chapter 3 and weight the pipeline timing results from the last section accordingly. First of all, we can estimate the probability of an instruction sequence occurring as the product of the probabilities of the two instruction types. For example, an EX/EX dependency occurs when there are two ALU operation
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