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Figure 9.3
DMA-managed I/O. DMA
manages the movement of data
between I/O and memory. |
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In programmed I/O, the processor is unable to do useful work after issuing an I/O request. Thus, a simple improvement is an interrupt-driven I/O (Figure 9.2) which allows the processor to initiate the I/O request and then resume work on the user program awaiting an interrupt from the I/O device. The I/O controller interrupts the processor when the data has been retrieved. Interrupt-driven I/O, while better than programmed I/O, still suffers from several limitations [270]: |
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1. The CPU must still manage the I/O transfer. |
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2. The CPU's interrupt handling ability places a limit on the I/O transaction rate. |
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The direct memory access (DMA) device is a further refinement that can independently manage the interface between the memory and the I/O device and its controller (Figure 9.3). Rather than each word going to the processor and then being forwarded to memory, as in the case of interrupt-driven I/O, a block of data can be transferred from an I/O device into memory by the DMA without affecting the CPU. When the entire block transfer is complete, the DMA sends an interrupt signal to the processor so that the processor is only involved at the beginning and the end of an I/O block transfer. As I/O traffic increases, the DMA traffic from I/O device to memory may occupy a significant amount of the bus bandwidth, slowing the processor down somewhat. |
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9.2.1 I/O Processors/Channels |
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The basic problem with DMA is not so much in its functionality, but rather in the limitations inherent in the structure of a bus that supports both processor and I/O device. As processors and I/O get faster, there is a need for a specialized processor-memory bus dedicated to synchronous high-speed data transfers. The system now resembles Figure 9.4. A synchronous bus is usually under the master control of the processor or a finite-state machine in the processor. Requests from the I/O processor are made to the bus control unit and once acknowledged initiate a high-speed synchronous data transfer from I/O processor to memory. The I/O processor now becomes a type of super-DMA using the synchronous processor bus. The I/O processor itself may be a rather general-purpose microprocessor, or it may be a specially designed processor to serve the I/O function. The latter is |
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