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Figure 1.4
Some processor registers and data paths. R indicates a register
in the register file, D an address displacement. |
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Implicit registers consist of the following (Figure 1.4): |
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1. Program or instruction counter (PC). Most instruction formats imply the next instruction in sequence as the current location plus the length of the current instruction. |
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2. Instruction register (IR). This register holds the instruction being interpreted or executed. Decoding is performed on the opcode held in this register. |
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3. Memory address register (MAR). This is the address register for a memory operation. |
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4. Storage register (SR). This is sometimes referred to as the memory buffer register, and contains the data used in the memory (to or from) operation. |
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5. Special use registersusage depending on instruction. |
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Data paths connect the output of one register to the input of another, and may include combinatorial logic. The opcode generally defines which of the many data paths are used in execution. The collection of all opcodes defines the data paths required by a specific architecture. A register may be connected to multiple output destination registers and accepts input from one of several source registers in any one cycle. A register output (Figure 1.5) is gated to various destinations with which it can communicate in a single cycle. The activation of a particular data path is done through a control point. The activation and definition of every control point in the processor for every cycle of operation is the responsibility of the instruction decoder, which may be implemented directly or as a microprogram storage (Figure 1.6). |
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