|
|
|
|
|
|
|
1. A certain processor (A) services jobs at a rate of 10 per second (with coefficient of variance, c2 = 1). It is proposed that another processor (B) be added to the system to improve the response time (Tw + Ts). The available processor (B) has a service rate of 5 jobs per second (c2 = 1). Jobs are to be dispatched with probability p to processor A, and with probability 1 - p to processor B. Use the M/M/1 open-queue model. |
|
|
|
 |
|
|
|
|
(a) If jobs arrive at 2 per second for service, find p. |
|
|
|
|
|
|
|
|
(b) If jobs arrive at 6 per second, find p. |
|
|
|
|
|
|
|
|
2. Now assume that in problem 1, the probability p an be adjusted based on queue size. Describe how p ould change with Q. |
|
|
|
|
|
|
|
|
3. Suppose we have four processors operating in a time multiplex SRMP. Each (L/S) processor has a four-phase instruction execution (IF - D/AG - EX/DF - PA). Since there is only one D/AG unit and one EX/DF unit, each processor accesses that unit once every four cycles. Each processor has a small integrated cache that it manages separately from the other processors. This cache has a 4% miss rate and 8-cycle miss time (1.5 refr per instruction). The execution units are fully pipelined (one operation per cycle). |
|
|
|
|
|
|
|
|
(a) For the "all in cache" (no miss) case, what is the performance of the four processors (instr per cycle)? |
|
|
|
|
|
|
|
|
(b) Considering cache misses, what is the performance of the four processors (instr per cycle)? |
|
|
|
|
|
|
|
|
4. Compare the performance in 3(b) to that of a single pipelined processor (decoding one instr per cycle) with a miss rate of 1% and branch delay of 2 cycles (frequency of branch is 20%). Run-on instructions take 4 cycles of execution (run-on delay is 3 cycles) and occur with frequency 10%. |
|
|
|
|
|
|
|
|
How effective in its use of parallelism must the SRMP processor in problem 3 be to provide an overall speedup over the pipelined processor described above? |
|
|
|
|
|
|
|
|
5. A certain shared bus multiprocessor (M processors) requires 8 bus cycles (processor cycle equals bus cycle) for a line transfer on a memory miss. If each processor executes at 1 CPI and has an integrated CBWA cache (W = .5), a miss rate of 2%, and 1.5 references per instruction, |
|
|
|
|
|
|
|
|
(a) Find the bus occupancy (r) for a single processor. |
|
|
|
|
|
|
|
|
(b) If we define bus saturation as processor time = n´bus transaction time (without waiting time), how many processors may be placed on the bus before saturation occurs? |
|
|
|
|
|
|
|
|
(c) If we have two processors on the bus, find B(n) and Tw (use model with request resubmission). |
|
|
|
|
|
|
|
|
6. Repeat 5(c) for four processors sharing the bus. What is the achieved bus transaction rate? What is the effect on processor performance? |
|
|
|
|
|