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Contemporary with the introduction of System/360 was the introduction of the Control Data 6600 in 1964. This was another very popular and widely recognized machine. It was one of the earliest load-store architectures, built about three types of register sets: address registers, integers, and floating-point registers. The 6600 series was a quite successful entry into the scientific marketplace and evolved over many years as a popular instruction set and was extended by Control Data in its 7600 and Cyber series machine lines. |
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The earliest L/S processor and what we now might call RISC processor was developed in the late 1970s at IBM research laboratories as the experimental 801 computer; see Radin [239]. It differed from the CDC 6600 in that it had uniform instruction size (32 bits) and it integrated the address and integer registers into a single set of 32 registers. Our L/S architecture, consistent with most mainframe and microprocessor usage, keeps floating-point registers separate from the other registers. On microprocessors, these floating-point registers were envisioned to be implemented in an associated co-processor. The first university-based L/S machine (and first use of the term RISC) was the RISC-1 work done at the University of California at Berkeley [230]. Further evolution of the RISC-1 led to RISC-2 and the introduction of register windows. RISC-2 was the basis for Sun Microsystems' SPARC instruction set. Other early RISC processor designs include Hewlett-Packard's Precision architecture, PA-RISC [183, 38], and the MIPS developed at Stanford [126], which became the basis for the MIPS R2000 and successor processors. |
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The register-memory architectures are dominated by the IBM mainframes, with program-compatible rival offerings from companies such as Amdahl, Hitachi, and Fujitsu. These architectures are a direct evolution of the System/360 architecture, extended over the years to include virtual addressing, enhanced storage capability, capability for addressing very large address spaces, etc. We have included in Figure 1.8 the Intel x86 series as an R/M machine. The Intel x86 series is an extension of its earlier microprocessor efforts such as its 8080 and 8086 [58], and it differs significantly from most other machines presented in this text. While it follows the R/M format, it does not have general-purpose registers. Rather, it uses a number of registers with designated special purposes. While it has 16 registers and one would expect that adequate software support would produce code whose characteristics would generally resemble a prototypical R/M, this correlation is only very approximate. |
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In 1967, Digital Equipment introduced its well-known PDP-11 series of 16-bit minicomputers [30]. This two-address instruction set accessed values and memory through the use of eight general-purpose registers. Memory was usually accessed indirectly through the registers. The registers had multiple functions. The exact function was determined by use of an associated register mode field. Each register specification had an associated 3-bit mode identifying one of eight possible uses of the designated registers. In 1978, DEC introduced a 32-bit extension called the VAX line. This is the motivation for our prototypical R+M architecture. VAX introduced a robust set of instruction formats, including register and memory formats for two- and three-address instructions. VAX designers continued the use of the register modes introduced in the PDP-11, as the VAX was to be upward-compatible from the PDP-11. The resultant design had byte-variable instructions with |
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