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Note 4 We assume a "copyback" strategy for writes to the cache. If the cache strategy were "write through," then the store would need 5 cycles of main memory access. These cache strategies are explained more fully in Chapter 5. |
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To execute this code fragment: |
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Number of instructions = 5 (1 RR, 4 RM). |
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Code size is the sum of the sizes of the single RR instruction2 bytes plus the four RM instructions (each 4 bytes), a total of 18 bytes. |
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The number of cycles to execute this sequence of instructions is simply the sum of the instruction times (11, 7, 14, 11, and 10 cycles)a total of 53. If there were no cache, this sum would increase to 77 cycles. On the other hand, if there were a cache and it had no misses, the execution time would be 45 cycles. |
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2. Assuming both code and data are resident in cache, show timing for (a) BCT R1, TARGET and (b) BAL R1, TARGET. |
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