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Finally, there is the issue of memory design for any of these organizations. Can large, second-level caches provide the appropriate bandwidth and operand supply for vector processors? Ultimately, the central question becomes one of optimizing performance for available silicon area for both the memory system and the processor design, given the best software technology. The multiplicity of technology and variables make the evolution of concurrent processors a particularly exciting area in computer design. |
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Data Note 1: The Vector Processor Model. |
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Vector processors have been well studied in the literature, and much of the data presented here uses models originally developed by Hockney and Jesshope [132] or Stone [272]. |
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Data Note 2: Multiple Instruction Execution. |
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The data presented in Figures 7.52 and 7.53 are based on the work of Acosta. They represent a small program sample. No compiler assistance is provided. |
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Reliability. Because the results are based on a small number of benchmarks, they should be viewed with caution. Reported results seem consistent, but compilers may play a significant role in the future in altering the results. |
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Stability. The variance is expected to be high, although detailed statistical studies have yet to be done. |
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7.11 Annotated Bibliography |
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One of the earliest vector processors was the Cray-1 from Cray Research. This was the first machine to make extensive use of vector registers. Most large scientific machines today are vector processors or, in the case of the mainframes, pipelined processors with optional vector processing adjuncts. Vector processors have been in production for close to twenty years. There is an extensive body of literature analyzing the advantages and limitations of these machines. The following three textbooks have extensive summaries of the literature on vector processors. |
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R. W. Hockney and C. R. Jesshope. Parallel Computers 2. Adam Hilger, Philadelphia, 1988. |
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H. S. Stone. High-Performance Computer Architecture. Electrical and Computer Engineering Series. Addison-Wesley, Reading, MA, 2nd edition, 1990. |
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P. M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill, New York, 1981. |
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