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Page 404 Then the effective processor performance is: Effective Performance (cycles per instr) = CPI (1 + flpTmiss), where CPI is the processor performance (cycles per instruction) without cache/memory delays. The relative performance is Other cache design parameters such as placement algorithm (e.g., degree of set-associative mapping), replacement algorithm, and prefetch strategy are less directly involved with the cache-memory interface. Their effects may be appropriately reflected through the miss ratio [259]. 6.8.6 Copyback Cache Study Assuming CBWA strategy and line-buffered I/O, all read and write cache misses result in line-read requests to the memory system, and the corresponding line-write requests if the lines are dirty and must be copied back. Ignoring I/O, there will be no queueing delay, as the processor will not make requests until memory is available. We consider the effects of I/O in study 6.3(d). In considering I/O, the processor is blind to its own traffic (Tbusy = 0) and thus can be affected only by the I/O traffic (li). Once the I/O traffic (li). is determined, Tw can be computed as discussed in the preceding section. All requests, I/O and processor-cache, are delayed by Tw, but only the processor-cache delays affect performance. Study 6.3 Evaluating Copyback (CBWA) Caches Assume a CBWA cache has a miss rate of 0.03 misses per reference with a dirty line ratio of 0.5. This cache is used with a processor that makes a reference every 40 ns (mean). Assume the cache is configured with: cache line size = 16B, Physical word size = 4B, and the memory is configured as: Ta = 120 ns, Tc = 100 ns, Tbus = 40 ns, m = 2. (a) Assume the cache writes a dirty line before reading lines (unbuffered) and that an entire line must be transferred to the processor before it resumes processing (these strategies are found in several microprocessor caches). What is the cache miss delay, ignoring I/O effects?
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