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Chapter 6
Memory System Design and Processor-Memory Models |
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In many processor design situations, the main memory system is the principal design challenge. It can be the most costly part of the processor electronics; moreover, it may go a long way in determining the overall effective or realized performance of the system. |
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There are two basic parameters that, at least in a general sense, determine memory systems performance. The first is the access time. This is the time for a processor request to be transmitted to the memory system, access a datum, and return it back to the processor. Access time is largely a function of the physical parameters of the memory systemthe physical distance between the processor and the memory system, or the bus delay, the chip delays, etc. The second parameter is memory bandwidth, the ability of the memory to respond to requests per unit of time. Bandwidth is primarily determined by the way the physical memory system is organizedthe number of memory modules and the use of special sequential accessing modes within a module. As processor ensembles can be quite complex, the memory system that serves these processors is correspondingly complex. |
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Figure 6.1 illustrates a general form of computer systems. It consists of multiple processors, each with its own private cache, connected to a memory system through a processor-memory interconnect. The processors may be of various kinds: well-mapped processors, pipelined processors, or even vector processors. |
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The memory consists of multiple memory modules, where each memory module is capable of performing one memory access at a time and contains a subset of the total physical address space. The memory modules are organized into memory banks. Each memory bank consists of multiple modules that share the same input and output buses. Consequently, within a memory bank, only one memory module is able to begin or complete a memory operation during any given bus cycle. Therefore, the memory bank organization is meaningful only if the memory cycle time is greater than the bus cycle time. |
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