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14. For an 8KB integrated level 1 cache (direct mapped, 16B lines) and a 128KB integrated level 2 cache (2W set associative, 16B lines) find the solo and local miss rate for the level 2 cache. |
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15. Show the directory layout of a 64KB sectored cache (two-way set assoc., 128B line, 8B transfer unit, 8B sub-line). Assume the processor address is 30 bits. Compute the total number of directory bits and compare with a non-sectored cache with 16B lines (otherwise similar). |
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16. Compute the instruction traffic per instruction for a scientific environment based on the following instruction timing templates described in chapter 4 (P = 64 bits). Use chapter 3 branch data. Assume guess in-line on BC. |
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(a) MIPSR2000 (L/S architecture). |
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(b) MIPS R4000 (L/S architecture). |
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(c) IBM 3033 (R/M architecture). |
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Assume a condition code is set at the end of the EX cycle. Ignore effects of delayed branch. |
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17. Consider the effect of changing line size on study 5.2. For 40, 50, and 60 ns CPU cycle times and for 4KB, 16KB, and 64KB compare the effect of a 64B and a 16B line with that shown in Figure 5.44. Other study assumptions remain the same. |
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18. A certain chip has area sufficient for an 8KB I-cache and a 4KB Dcache, both direct mapped. The processor has a virtual address of 32b, real address of 26b, and uses 4KB pages. It makes 1.0 I-refr/I and 0.5 D-refr/I The cache miss delay is 5 cycles plus 1 cycle for each 4B word transferred in a line. The processor is stalled until the entire line is brought into the cache. The D-cache is CBWA, use dirty line ratio w = 0.5. Both caches are user-only environment with R/M architecture and line size of 64B. Find: |
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(a) The CPI lost due to I-misses and the CPI lost due to D-misses. |
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(b) For the 64B line, find the number of I- and D-directory bits and corresponding rbe (area) for both directories. |
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(c) Find the number of colored bits in the I-cache and D-cache. How many ''free" page lists are required to ensure V = R? |
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