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Page 342 4. Plot traffic (in bytes) as a function of line size for a DTMR cache (CBWA, LRU, scientific environment, R/M architecture) for: (a) 4KB cache. (b) 32KB cache. (c) 256KB cache. 5. Suppose we define the miss rate at which a copyback cache (CBWA) and a write-through cache (WTNWA) a have equal traffic as the crossover point. (a) For the DTMR cache, find the crossover point (miss rate) for 16B, 32B, and 64B lines. To what cache sizes do these correspond? (b) Plot line size against cache size for crossover. 6. The cache in problem 1 is now used with a 16b line in a transaction environment (Q = 20,000). (a) Compute the effective miss rate. (b) Approximately what is the optimal cache size (the smallest cache size that produces the lowest achievable miss rate)? 7. In a two-level cache system, we have: L1 size 8KB with 4w set assoc., 16B lines, and WTNWA and L2 size 64KB direct mapping, 64B lines, and CBWA Suppose the miss in L1, hit in L2 delay is 3 cycles and the miss in L1, miss in L2 delay is 10 cycles. The processor makes 1.5 refr/I. (a) What are the L1 and L2 miss rates? (b) What is the expected CPI loss due to cache misses? (c) Will all lines in L1 always reside in L2? Why? 8. A certain processor has a two-level cache. L1 is 4KB direct-mapped, WTNWA. The L2 is 8KB direct-mapped, CBWA. Both have 16-byte lines with LRU replacement. (a) Is it always true that L2 includes all lines at L1? (b) If the L2 is now 8KB 4-way set associative (CBWA), does L2 include all lines at L1? (c) If L1 is 4-way set associative (CBWA) and L2 is direct-mapped, does L2 include all lines of L1? 9. Suppose we have the following parameters for an L1 cache with 4KB and an L2 cache with 64KB. The cache miss rate is: 4KB 0.10 misses per refr 64KB 0.02 misses per refr 1 refr/I 3 cycles L1 miss, L2 hit 10 cycles total time L1 miss, L2 miss
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