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J. M. Mulder, N. T. Quach, and M. J. Flynn. An area model for on-chip memories and its application. Journal of Solid State Circuits, 26(2), February 1991. |
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S. Przybylski, M. Horowitz, and J. Hennessy. Characteristics of performance-optimal multi-level cache hierarchies. Proceedings of the 16th Annual Symposium on Computer Architecture, pages 114121, June 1989. |
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Working Sets and Workload |
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L. Balady and C. Kuehner. Dynamic space sharing in computer systems. Communications of the ACM 12(5), May 1969. |
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P. Denning. The working set model for program behavior. Communications of the ACM, 11(5):323333, 1968. |
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P. Denning. Working sets past and present. IEEE Transactions on Software Engineering, SE-6(1):6484, 1980. |
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A. Smith. Cache evaluation and the impact of workload choice. Proceedings of the 12th International Symposium on Computer Architecture, pages 6473, June 1985. |
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1. A 128KB cache has 64B lines, 8B physical word, 4K pages, and is four-way set associative. It uses copyback (allocate on write) and LRU replacement. The processor creates 30-bit (byte-addressed) virtual addresses that are translated into 24-bit (byte-addressed) real byte addresses (labeled A0A23, from least to most significant). |
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(a) Which address bits are unaffected by translation (V = R)? |
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(b) Which address bits are used to address the cache directories? |
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(c) Which address bits are compared to entries in the cache directory? |
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(d) Which address bits are appended to address bits in (b) to address the cache array? |
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2. Show a complete layout of the cache in problem 1. Present the same detail as in Figures 5.5 through 5.7. |
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3. Compute the effective miss rate for the cache in problem 1, assuming a single user and R/M processor architecture without systems or I/O effects. |
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