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5.21 Some Areas for Further Research |
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While it may appear that uniprocessor caches have been well-studied, data in certain areas, such as miss rate for very large caches, is still limited. The behavior and miss rate under various systems and I/O disciplines have really not been fully explored. The major research thrust for caches is supporting multiprocessor configurations. Here there are many additional issues, including the various protocols required to maintain consistent data images across multiple caches, as well as the associated bus traffic to support this consistent data image. |
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The first mention of the concept of a transparent buffer memory appears to be by Wilkes in 1965 [306]. The earliest reported data on the effectiveness of cache-type buffers is from Gibson [102]. Gibson, Pomerine, and Conti, all of IBM, provided the early basis for cache-type buffers. The System 360/Model 85 [56] was the first commercial processor to effectively incorporate cache memory. Much of the data in this chapter has been derived from the work of Smith, Clark, and Hill, in addition to earlier studies. When dealing with statistical adjustments, the derivation of comparable data can be quite difficult, as the data reported are based on incomparable work loads. Thus, in using the work of Agarwal or Mitchell, for example, we have had to normalize their data to the expected DTMR. This naturally involves some uncertainty. The adjustments, therefore, are always less reliable than the basic DTMR data. |
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Analytical models for cache have been proposed, which could in principle resolve a good deal of the uncertainties in dealing with empirical data. Unfortunately, these models largely rely on the availability of statistical parameters that are also quite difficult to obtain and are workload-dependent. |
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Data Note 1: Design Target Miss Rate (Figures 5.10, 5.28, and 5.29). |
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Design target miss rate (DTMR) was first introduced by Smith [262, 260]. Based on extensive program traces from eight different workloads (mostly S/370 and VAX traces), Smith [262] gave DTMR for cache size ranges from 32 bytes to 32K bytes. In [260], Smith also listed DTMR for 16-byte line caches (for cache size up to 64K bytes). Following the methodology used in [262], DTMR in the higher range (128K and 256K) are determined from additional data (16-, 32-, and 64-byte line caches for cache size up to 256K bytes) given in Hill [129]. DTMR for 128-byte line cache in the 128256K cache size range are extrapolated from existing data and should be used with caution. |
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Use of the data. The data in Figure 5.10 should be used in conjunction with the adjustment data (Figures 5.135.14) to determine the effective miss rate for integrated caches. The adjustment process is described in the text. |
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Reliability. As described previously, the data presented in Figure 5.10 has been based on many sources and should represent a good design basis. Data for large caches is based upon a smaller sample and is less reliable. |
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