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5.19.2 Cache/TLB Excess CPI Design Rules |
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1. Find effective miss rate per reference (see cache evaluation design rules). |
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3. Compute DF/I (with WTNWA) or (DF + DS)/I (with CBWA). |
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4. Find memory miss penalty (also see discussion in chapter 6). |
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5. Excess CPI due to cache is: |
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(Miss rate)(references/I)(Miss penalty in cycles). |
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6. Find the "not in TLB" rate per instruction (Figure 5.46). Multiply by references per instruction. No further adjustments are needed. |
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7. Excess CPI due to TLB is: |
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(Not in TLB rate)(TLB miss penalty)(references per instruction). |
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8. Excess CPI is sum of (5) and (7). |
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Caches operate on the principle of spatial and temporal locality. Regions and words of memory that have been recently accessed will probably be accessed again in the near future. The effect of the cache is to provide the processor with a memory access time equivalent to that of a high-speed buffer, and significantly faster than the memory access time would be without the cache. Without a cache, the processor instruction timing template would be significantly extended, and the effects of the memory system on pipeline breaks such as branches would become much more pronounced. Thus, the cache is an important constituent in the modern high-speed processor. The design target miss rate (DTMR) provides a basic objective for cache designers in achieving overall processor performance. The DTMR may be adjusted for various factors, such as the architecture, the operating system, the system's environment, and I/O effects, to give an overall effective or adjusted DTMR. Each environmental factor, such as the system or the processor architecture, requires an adjustment to the DTMR so that the effects of various working set differences are properly accounted for. |
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The processor architecture in particular affects not only the miss rate by affecting the working set size, but it directly affects the processor traffic to the cache (the number of references per instruction). These effects must be carefully incorporated into any performance model to correctly determine processor-cache interaction. |
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This chapter addresses only the effect of cache on a single processor. In a later chapter we will see more on cache and the role it plays in multiprocessor configurations. |
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