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Page 315 Table 5.7 Expected Processor Data Traffic per Instruction Architecture Scientific Commercial P = 4 P = 8 Read Write Read Write Read Write L/S 0.31 0.19 0.47 0.22 0.47 0.22 R/M 0.34 0.21 1.35 1.19 0.92 0.76 R+M 0.52 0.32 1.35 1.19 0.92 0.76 Table 5.8 Expected data traffic (R/M and R+M) created by variable-length operations instructions (commercial environment). P = 4 P = 8 Type Freq. per 100 HLL ops Length (bytes) Reads Writes Reads Writes Move Character 16 33 9 9 5 5 Move Decimal 7 4 1.75 1.75 1.38 1.38 Compare,a etc. 22 4 1.75 1.75 1.38 1.38 Decimal arithb 6 4/3 3.25 1.75 2.63 1.38 Total per 100 HLL ops 214 205 136 128 a as specified (assuming prefetch). b write goes to longer operand (4B). For the R/M architecture, we would expect the same number of reads or writes from memory per HLL operation. This increases the data traffic by the decrease in R/M instructions per 100 HLL operations: 200/180, or for R/M traffic, we have: Data reads/I = 0.34 Data writes/I = 0.21 For a scientific environment, the data traffic per instruction is summarized in Table 5.7. To evaluate data traffic for a commercial environment, we need to assess the traffic created by MM operations. The memory-to-memory (MM) operations require a bit more analysis, since usually such operations are only byte-aligned, not aligned with respect to the data paths of the processor. Also, there are two types of MM instructions: two-source operand and one-source operand. The one-source operand (such as in MOVE.C) takes (reads) an operand in memory, then writes it back into memory. Each memory access takes:
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