Figure 5.18
Effect of write policy on memory traffic.
1. WTNWA: Write-through (no write allocate), at 5% miss rate.
100 instructions create 200 references (168 read references and 32 writes). This creates 8.4 read misses or traffic of 8.4 ´ 8 physical words plus 32 write references. (Assume each takes a physical word.)
Write-through total: 67.2 + 32 = 99.2 actual references.
Memory traffic = 99.2/200 = 0.50.
2. CBWA: Copyback (write allocate), at 5% miss rate.
100 instructions now create 200 cache references and thus 10 misses, but 3 of these require a line write (since this is an integrated cache, we assume that 30% of all lines are dirty). Thus, 13 ´ 8 = 104 actual references.
Conclusion: A 5% miss rate is nearly the crossover point. (See Figure 5.18.) For lower miss rates, copyback reduces memory traffic, while for higher miss rates, write-through reduces memory traffic.
5.7 Strategies for Line Replacement at Miss Time
What happens on a cache miss? If the reference address is not found in the directory, a cache miss occurs. Two actions must promptly be taken: (1) the missed line must be fetched from main memory; (2) one of the current cache lines must be designated for replacement by the currently accessed line (the missed line).
