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Figure 5.9
Design target miss rate (DTMR). |
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Cache size is the primary determinant of cache performance (miss rate). The larger the cache, the lower the miss rate. Almost all cache miss rate data is empirical, and as such has certain limitations. Data based upon older machines, where the memory size was fixed and small, shows the working set being captured by relatively small size caches, since these caches are significant in size relative to the original memory size for these programs. Thus, there is a tendency for the reported miss rate of a particular cache size to increase over reporting time. This is simply the result of measurements made on programs of increasing size. Notwithstanding the difficulty in producing stable design data, Smith [260] has developed a series of design target miss rates (DTMR) that represent a conservative estimate of what a designer should expect from an integrated (instruction and data) cache. These data are presented in Figure 5.10, which covers cache sizes to 256 KB. The data points in this figure represent design target miss rates per reference to memory. They are based upon demand fetch, copyback cache with LRU (least recently used) replacement. Except for 4-and 8-byte line sizes, the data is for a fully associative cache. In the case of 4-and 8-byte line sizes, four-way set associative cache is assumed. The figures show that for large caches, large block sizes or line sizes perform best, the crossover point being about 48KB. Large line sizes have better spatial locality and hence reduce the miss rate. Smaller caches have better performance with smaller line sizes. Since there simply are not enough localities captured in the cache with large line sizes, there are not enough temporal localities in the small cache with a large line size. Large line sizes have an added disadvantage not reflected in these figures: increased memory traffic. For example, 4KB both at 64-and 128-byte line sizes give approximately the same miss rate, but the 128-byte line size creates twice as much memory traffic per missrequiring twice as many bytes to be transferred from memory to cacheto support its operation. |
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Figures 5.11 and 5.12 show the design target miss rates in light of other studies. In all cases, the design target miss rates represent conservative expectations of cache performance. Some of the studies (e.g., S/360 and CDC 64000) were based on address traces of older machines that did not have cache. As expected, systems code represents the largest overall body of |
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