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24b real address |
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8B physical word |
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64B line |
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\ 256 lines |
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Simultaneous access to TLB directory, and array. |
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Has simultaneous access of directory and array. |
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Improves locality (hit rate), since now line may lie in one of four locations. |
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Fewer higher-order bits involved in directory access. (If only lowest 12b are involved, the TLB access can occur simultaneously with cache access, since lower bits are unaffected by TLB.) |
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Uses smaller RAM sizes. |
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Additional compress/multiplexing may incraese cycle time. |
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1. Translate VPN to RPN with TLB (not shown). |
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2. Access cache array sets and cache directory entries to ensure correct line is in cache. |
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3. Compare tags from directory (12b) with tag address bits. |
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4. If compare valid, select corresponding set and MUX data to processor. |
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