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Table 1.10 Instruction set mnemonic elements.
MnemonicOperation
ADDAddition
SUBSubtraction
MPYMultiplication
DIVDivision
INCIncrement
DECDecrement
CMPCompare
MOVEDecimal (.P) or Character (.C) Move
CLRClear (a register)
LDLoad (a register from memory)
STStore (a register to memory)
LDALoad address (generated by instr) into register
LDMLoad multiple registers
STMStore multiple registers
MOVEMove (register to register or memory to memory)
SHLShift Left
SHRShift Right
BRUnconditional Branch
BCConditional Branch
BALBranch and Link
BALRBranch to Register and Link

merely indicate some of the generic operations used throughout the text and provide a general framework.
Many commercial assemblers allow the programmer to specify the operand, and the assembler infers the data type from its knowledge of the operands. Thus, if the location someLoc were defined to be a double-precision floating-point value, then the instruction LD R15, someLoc would generate the identical code as LD.D R15, someLoc. Additionally, when there is no explicit type information in the instruction, as in MPY R2, R14, R4, the assembler assumes that the data type is a standard machine word, and thus the instruction generated is the same as MPY.W R2, R14, R4. In this book, the goal is clarity, and thus a formal data type is usually appended to the operation mnemonic.
Register usage is clear from contexta binary operation (such as addition) is a three-operand instruction if there are three operands, a two-operand instruction if there are two operands, and similarly for unary operations. The first register (or memory address) specified is the destination; this reflects the similarity with algebraic notation. Thus, the instructions specified by DIV.WA, B would generate the result A = A DIV B, and those specified by NOT.W A, B would generate the result A = NOT B. These conventions are summarized in Table 1.13.

 
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