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2. The physical word size (Figure 5.4), or the transfer unit between CPU and the cache. |
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The primary measure of cache performance is the miss rate. This is the probability of a reference made to the cache that is not found in the cache. The miss rate times the miss time measures the delay penalty due to the cache miss. m most processor designs, the processor ceases activity when a cache miss is encountered. Thus, a cache miss behaves in much the same way as a pipeline break. |
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Cache Operation and Information Theory |
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An alternative view of the operation of cache memory is that caches work because of redundancy in the sequence of address requests made to memory by the processor. It is this redundancy that allows the simple demand fetch hardware algorithm to accurately predict the future reference requirements of the processor. In a now well-known study on the subject, Hammerstrom [120]showed that there was generally no more than about 1% information content in an address trace. Given knowledge of past references, 99 bits out of every 100 bits of address reference made by the processor to the memory system are predictable. The remaining bit of information represents the occurrence of references to new localities undeterminable until the time of program execution. |
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A cache may be organized to fetch on demand or to prefetch data. The former organization, usually referred to as demand fetch organization, is the most commonly used and the one that is the focus of this chapter. As the name implies, a demand fetch cache brings a new memory locality into the cache only when a processor reference is not found in the current cache contents (a miss occurs). The prefetch cache attempts to anticipate the locality about to be requested by the processor and thus prefetches it into the cache. The prefetch cache has only marginal advantage over a demand fetch cache [259]. Its use is usually restricted to certain I-cache applications. |
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Within the cache, there are three basic types of organization: (fully) associative mapped (Figure 5.5), direct-mapped (Figure 5.6), and set associative mapped (Figure 5.7, which is really a combination of the other two), m fully associative mapping, when a request is made to the cache, the requested address is compared in a directory against all entries in the directory. If the requested address is found (a directory hit), the corresponding location in the cache is fetched and returned to the processor; otherwise, miss occurs. |
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In a direct-mapped cache, lower order line address bits are used to access the directory (index bits in Figure 5.8). Since multiple line addresses map |
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