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As mentioned in chapter 1, the memory system consists of a hierarchy of storage elements (Figure 5.1). Excluding the register set, the cache has the shortest access time, or latency, of all the levels of the storage system, and the highest bandwidth. The goal of an effective memory system is that the effective access time that the processor sees is very close to t0, the access time of the cache. Most accesses that the processor makes to the cache are contained within this level. The achievement of this goal depends on many factors: the architecture of the processor, the behavioral properties of the programs being executed, and the size and organization of the cache. |
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Caches work on the basis of the locality of program behavior [117]. There are three principles involved (Figure 5.2): |
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1. Spatial Locality Given an access to a particular location in memory, there is a high probability that other accesses will be made to either that or neighboring locations within the lifetime of the program. |
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2. Temporal Locality This is complementary to spatial locality. Given a sequence of references to n locations, there is a high probability that references following this sequence will be made into the sequence. Elements of the sequence will again be referenced during the lifetime of the program. |
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3. Sequentiality Given that a reference has been made to a particular location s it is likely that within the next several references a reference to the location of s +1 will be made. Sequentiality is a restricted type of spatial locality and can be regarded as a subset of it. |
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Locality is a characteristic of most programs, but it is significantly influenced by the program representationthe architecture. The cache designer must deal with the processor's architecture and accessing requirements on the one hand, and the memory system's requirements on the other. Effective cache designs balance these two factors within the cost constraints of the cache design itself. |
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