< previous page	page_257	next page >
Page 257 in-line, the CC is set at the end of the cycle in which * + 1 should have been decoded. In this simple processor, we assume that decode is not performed until CC is set. This results in a delay of one cycle each time a BC fails (goes in line). This adds a delay of Prob ((BC) and in line)(one cycle) = .104 ´ .46 ´ 1 = 0.05 CPI. Thus, address dependencies can be caused by any of the following: LD--LD, LD--ST, LD--BR, LD--BC. We can estimate the occurrence of these events by making the assumption that these instructions occur with independent probability; then: Prob of dependency event = Occurrence of LD preceded by LD/ST/B = (Prob LD)(Prob LD/ST/B/) = .3 (.605) = .18 However, simply the occurrence of a potential address dependency does not mean that there is an actual dependency. In a LD-LD instruction pair, not every leading LD references a register used in the subsequent LD address computation. In fact, we know from Table 3.19 that the actual dependency occurs with frequency 0.099. So, the net frequency of an address dependency is: Prob fo address dependency = 0.18 × 0.099 = 0.02 and Delay due to address dependency = 0.02 (1.0) cycle delay = 0.02 CPI delay For run-on instructions, we simply sum up the execution times of each of the run-on instructions and weight that execution time by their frequency of execution. The run-on instructions that we consider for the baseline processor are: Instruction Execution time Run-on time MPY.W 3 cycles 2 cycles DIV.W 15 cycles 14 cycles ADD.F 3 cycles 2 cycles MPY.F 3 cycles 2 cycles DIV.F 15 cycles 14 cycles
< previous page	page_257	next page >