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| Table 4.17 Stages. | | Stage.W | Stage.WR | Register to be Written by Instr | | A.W | A.WR | in AG stage | | T.W | T.WR | in T stage | | F.W | F.WR | in DF stage | | E.W | E.WR | in EX stage |
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When this instruction passes to the AG stage, it becomes A.W and A.WR. |
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If a pipeline stage is empty, the W bit is false (=0). In the EX cycle, there is another field, E.LAST, which indicates whether this is the last cycle of execution for the current instruction; this information is needed to control the bypass. |
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Thus, suppose the instruction |
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ADD R1,D[R2,R3] |
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enters the decoder. It generates a one- and a four-bit field: |
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As this instruction passes into different pipeline segments (assume only one instruction in a segment at a time), this information is transferred to the stage interlock controller for that segment. Since there are four segments involved, we need four 5-bit registers to hold this information: |
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As the preceding ADD instruction passes from stage to stage, its stage interlock information is shifted down one position until execution is complete. |
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In the D stage, the following signals are also available: |
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| D.B2 | Base register field from the instruction. | | D.X2 | Index register field from the instruction. | | D_use_B2 | Signal indicating whether B2 register is needed for address. | | D_use_X2 | Signal indicating whether X2 register is needed for address. |
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Note that D_use_B2 and D_use_X2 are false if the respective register field in the instruction is zero, since register 0 is never used for address generation. |
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