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Page 247 Table 4.16 Signals. Signal Size Produced by Meaning D.B2 4b IR Base register field from instruction. D.X2 4b IR Index register field from instruction. D_use_B2 1b Decoder Is B2 register used by this instruction? Y=1, N=0. D_use_X2 1b Decoder Is X2 register used by this instruction? Y = 1, N = 0. Stage.W 1b Decoder Does decoded instruction write into the register set (GPR)? Y=1, N=0. Stage.WR 4b Decoder GPR number to be written. with action: R1 ¬ R1 OP Mem [[B2] + [X2] + D2] and where R1, B2, and X2 each point to one of 16 general-purpose registers (GPRs). We assume that the register file includes bypass logic. Specifically, if a particular register is being written and read in the same cycle, the register file automatically detects this and bypasses the new value as the result of the read. In the copy of the register used for address generation, we assume that reading register 0 always results in a value of zero. A typical address generation dependency (without the bypass) has the following timing: As shown, the load instruction can successfully read R1 for address generation in the same cycle as the PA for the add, resulting in a three-cycle delay. The decoder uses or produces the signals shown in Table 4.16. This pipeline may have hard-wired control or microcode. In either case, during decode, the logic determines whether the instruction (or microinstruction) writes a GPR in the PA cycle. This information is carried along to each stage of pipeline in two fields of information. In each stage other than D, there is a field named Stage.W that indicates whether the instruction in the stage writes a GPR, and another field named Stage.WR that provides the four-bit identifier of that GPR. Stage.W and Stage.WR (Table 4.17) are generic labels for register use designators produced by the decoder for each instruction in the pipeline. An instruction in the decoder produces: Stage.W Stage.WR
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