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Suppose we have the following sequence of two ADD instructions, in which (2) depends on (1). We look at the effect of ALU bypass on instruction (2). |
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4.6.3 Address Generation Interlocks |
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An address generation interlock (AGI) condition exists whenever an instruction requires a register for its operand address calculation but the register is unavailable because it will be written by some preceding, uncompleted instruction. (See previous examples.) |
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A pipeline designer can reduce, and in some cases eliminate, address generation delays by incorporating bypasses at appropriate points in the pipeline. As in the example, an address generate bypass routes an ALU value (EX) or a DF value directly to the address generator (without PA). We may estimate this effect by using the data in Table 3.19. For example, if there were three stages between address generation (AG) and putaway (PA), then the performance degradation experienced without bypassing (as seen in Chapter 3) would be: |
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| = 3-cycle loss ´ 0.099 = .297 | | | = 2-cycle loss ´ 0.084 = .168 | | | = 1-cycle loss ´ 0.028 = .028 | | | = 0-cycle loss | | |  |
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Total delay = 0.493 |
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| cycles/instruction. |
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