|
|
|
|
|
|
|
of the outcome of the branch. Any such instructions must be issued conditionally subject to the outcome of the setting of the condition code. Thus, such instructions may generate addresses and fetch data, but must not enter execution (or at least certainly not putaway) to prevent altering established data in the case of a mispredicted outcome of the condition code. For the simple type of machines considered here, this is not a severe restriction and does not cause any additional delay. It becomes a more serious concern with more sophisticated instruction-issuing mechanisms considered later. |
|
|
|
|
|
|
|
|
3. The decoder is assumed to use a static prediction mechanism. It predicts the outcome of a conditional branch based upon the particular type of branch encountered, using data presented in Chapter 3. |
|
|
|
|
|
|
|
|
Unlike simple branch processing used in previous studies, it is possible to predict a path following a branch and proceed with D, AG, and DF (but not PA or EX if it includes PA). Since a bigger savings occurs when the in-line path is successfully predicted, that path is guessed even if the target path actually occurs more frequently. Thus, up to a point it is better to guess in-line, even though it is frequently wrong. |
|
|
|
|
|
|
|
|
There are secondary issues, however. Branch prediction carries the penalty of increasing I-references. These extra I references might cause a cache or TLB miss. A miss causes suspension of processing while code or a virtual address (which might not have been needed) is readied. |
|
|
|
|
|
|
|
|
Ignoring secondary issues, for an R/M architecture with the following template, we want to find the minimum probability of target path selection for which it is better to predict the target path. |
|
|
|
|
|
|
|
|
The first issue to be considered is the I-buffer (IB) configuration. From the earlier discussion, we can avoid a run-out delay if the in-line path has the following number of IB entries: |
|
|
|
|
|
|
|
|
Since (from Table 3.2) the typical R/M instruction length is less than 4B, there are more than two instructions in an 8-byte IF. Only two 8B buffers are required. We assume one double word (8B) of target is also available. |
|
|
|
|
|
|
|
|
At issue is determining the strategy (guess in-line or guess target) to minimize the expected branch penalty. |
|
|
|
|
|
|
|
|
Now compute the four penalties: |
|
|
|
|
|
|
|
|
(a) Guess in-line and the code goes in-line. |
|
|
|
|
|
|
|
|
(b) Guess in-line and the code goes to the target. |
|
|
|
|
|
|
|
|
(c) Guess target and the code goes to the target. |
|
|
|
|
|
|
|
|
(d) Guess target and the code goes in-line. |
|
|
|
|
|
