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Figure 4.15
Instruction buffer. |
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Figure 4.16
Instruction prefetch mechanisms. |
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An I-buffer is designed to take advantage of the sequentiality of instruction fetch references between taken branch instructions. The instruction buffer consists of one or more prefetch registers (PFR), as shown in Figure 4.15. The width of each register is normally some multiple of the unit of access (word, doubleword) from the memory system. The first PFR, PFR(1), is the instruction register (Figure 4.16) and contains the instruction word that is currently being decoded. The prefetch unit attempts to keep the remaining PFRs filled with the instructions that follow the one being decoded. When the instructions in PFR(1) have been used, the contents of the remaining PFRs are transferred to the immediately preceding PFR, and a memory fetch is initiated to fill the last PFR, which is now empty. (In practice, a circular buffer with a pointer to the next available PFR is used.) When a successful branch occurs, all of the prefetch registers in the unsuccessful path become useless and memory fetches must be initiated to refill them. Instruction decoding resumes as soon as PFR(1) is loaded and continues as long as it is not empty. |
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