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Figure 4.14
I-buffer components. |
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4.4.5 Buffers Designed for Maximum Request Rates: The I-Buffer |
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The I-buffer (sub-unit B in Figure 4.12, page 213) contains the following features (Figure 4.14): |
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1. An instruction register. This register holds the instruction being decoded. |
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2. An alternate path buffer (or target buffer). When a branch is encountered and its outcome is unknown, the "DF" cycle is used to access the target path. If the branch is known (or guessed) to go to the target path, this buffer holds the previous requested in-line instructions. |
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3. A primary path buffer. This is the buffer that accesses in-line instruction words. On a branch, this buffer continues to fetch in-line instructions unless the outcome is known (or guessed) to go to the target path. Then branch target instruction words are retrieved into this buffer. |
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Each entry in the buffer holds an IF. The alternate path buffer usually holds only one or two "words" or IF accesses, while the primary path buffer should be large enough to avoid run-out (discussed next). |
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The selection of a branch direction is done by the decoder (sub-unit C). For each branch type (and mask combination if appropriate), the decoder may have a predetermined strategyeither to fetch the in-line or target path. We will see more of this in a subsequent section. |
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The first problem in designing a pipeline is to ensure a steady flow of instructions to the initial stage of the pipeline. Even when the memory bandwidth is sufficient to sustain the instruction flow, the memory access time requires multiple cycles. For this reason, we introduce an intermediate buffer in order to maintain the pipeline rate. This intermediate buffer is referred to as a prefetch register, or simply an instruction buffer or I-buffer. |
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If the I-buffer is of insufficient size, it is unable to mask out the accessing delay of sequential IFs. This results in an additional delay (in addition to the IF itself) in performing the fetch. This delay is called runout. |
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