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In this case, TI + 1 decode is delayed 6 cycles. If the branch is equally likely to go in-line as it is to take the target (TI), then the effective penalty is 5.5 cycles. |
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(ii) The effects of the unconditional branch (BR) can be similarly evaluated: |
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For this case, the penalty is 4 cycles. |
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Now, assuming the frequency of conditional branch is 15% and unconditional branch is 5%, we can compute the effect of branches on processor performance. |
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1 (decode) + .15(5.5) + .05(4), |
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1 + 0.825 + 0.20 = 2.025. |
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(iii) Consider the effect of address dependencies: |
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LD R5, ALPHA[R6,R7]
LD R6, BETA[R5,R7] |
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This results in a 3-cycle penalty. Similarly, |
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ADD R5, ALPHA[R6,R7]
LD R6, BETA[R5,R7] |
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Assume a 3-cycle penalty occurs in 4% of the instruction executions and a 5-cycle penalty occurs 1.5% of the time. We now have performance: |
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2.025 + 0.04(3) + 0.015(5), |
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