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Page 204 Table 4.6 Dependencies and delays. Instr Number Instr Dep. Dependency Marginal Delay Total Delay1 2 1 ® 2 address2 3 3 3 2 ® 3 data3 0 3 4 3 ® 4 data4 0 3 5 4 ® 5 Branch 0 3 6 5 ® TI No branch procedural 7 10 6 5 ® 6 procedural 3 6 1 Marginal delay is the delay between the currently scheduled cycle for an action and the actual occurrence of that action and following instruction. Total delay is the sum of the marginal delays, and is related to the pipeline's overall efficiency. We compute the total delay with respect to the originally scheduled (instruction 1) actions and the marginal delay with respect to the current instruction's scheduled actions (where they differ). 2 An address dependency exists because register 4 must be loaded before it is used in an address calculation. This causes instruction 2 to delay until register 4 is loaded. 3 A data dependency exists because register 3 must be loaded before it is executed upon. This causes instruction 3 to delay its EX until register 3 is loaded. 4 A data dependency exists because register 3 must be calculated before it is stored. This causes instruction 4 to delay its DS until the previous instruction's calculation has been stored in register 3. Assumptions: 1. The primary sources of delay are the branch, data dependencies, and run-on instructions. 2. The memory system is ideal. The performance we compute ignores cache access contention, cache miss effects, and memory access delay due to interference. Moreover, for this study, we assume a simple pipelined processor, i.e.: 1. There is a simple in-line instruction buffer. Each in-line instruction has its own instruction fetch (IF) from cache. There is a one-entry target instruction buffer for use with branch instructions. 2. There is no branch prediction mechanism. On the occurrence of a conditional branch (whose outcome is unknown), decoding of subsequent instructions ceases until the condition code (CC) is set. Later studies in the chapter examine more complex processors with additional features. The overall effect of dependencies on performance is to raise the CPI from an ideal of 1 cycle per instruction to:
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