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Figure 2.40
Computer architecture and its implementation: the
instruction set is a tradeoff between decoder
complexity and code density. |
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As a general rule, instruction sets that have more formats and more variability in instruction size have fewer instructions to execute overall than instruction sets with less variability. |
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The Marginal Utility of Code Density |
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As mentioned earlier, there is a basic instruction set tradeoff between code density and the effect of code density on storage hierarchy, especially the instruction cache (I-cache). Well-encoded instruction sets such as the R/M or R+M instruction sets use more decoder area, but provide a better level of I-cache performance. A more densely encoded instruction set requires fewer bits to be fetched from memory to execute a program than a less well-encoded instruction set. Consider our three base architecture typeswe assume for the moment that they all have the same ALU vocabulary. (This is basically true for the scientific environment.) If we add an I-cache (Figure 2.41), then all architectures improve because of improved average memory access time. |
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As we shall see in chapter 3, we expect to have the following relative instruction count for our three architectures: |
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| Load/Store | 1.0 | | Register/Memory | 0.9 | | Register+Memory | 0.6 |
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Accounting for instruction size differences, the approximate relative dynamic instruction traffic would be: |
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