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Page 80 Figure 2.15 The ith pipeline segment. Figure 2.16 Stage propagation delay. pipelining to describe the use of minimum delay to reduce cycle time. We exclude the register delay from both Pmax and Pmin. Let us define C as the delay due to clocking, which consists of both setup and register delay time for the input data. For the sake of this discussion, we ignore the effects of clock skew (i.e., we assume k = 0). Suppose the first data item set enters the ith stage (Figure 2.15) at absolute time t1. What is the earliest time (t2) at which we can safely enter a second data set? t2 + Pmin³ t1 + Pmax + C. That is, the second data set can be entered into the ith stage after the first data set has a guarantee of being safely stored into the register (Figure 2.16). Thus, t2 - t1³ Pmax - Pmin + C. The cycle time Dt is the minimum difference between t2 and t1, i.e., Dt = t2 - t1, so Dt ³ Pmax - Pmin + C. For any segment i: Dti = Pmini - Pmini + Ci = (Pmax - Pmin + C)i. Next, we determine the worst (or maximum) Dti across all segments. That is, Min cycle time = {max (Dti)}.
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