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Table F.11 Dragon CPU actions.
StateRead HitWrite HitRead MissWrite Miss
InvalidN/AN/AIssue bus read. If shared, next state = Shared-Clean; otherwise next state = Valid-Exclusive.Issue bus write miss. Write data to cache. If shareda, next state = Shared-Dirty, issue bus writeb; otherwise next state = Dirty.
Valid-Exclusive (or Read Private)Supply data to processor. Next state = Valid-Exclusive.Write data to cache. Next state = Dirty.Issue bus read. If shared, next state = Shared-Clean; otherwise next state = Valid-Exclusive.Issue bus write miss. Write data to cache. If shared, next state = Shared-Dirty, issue bus write; otherwise next state = Dirty.
Shared-CleanSupply data to processor. Next state = Shared-Clean.Issue bus write. If shared, Next state = Shared-Dirty; otherwise next state = Dirty.Issue bus read. If shared, next state = Shared-Clean; otherwise next state = Valid-Exclusive.Issue bus write miss. Write data to cache. If shared, next state = Shared-Dirty, issue bus write; otherwise next state = Dirty.
Shared-DirtySupply data to processor. Next state = Shared-Dirty.Issue bus write. If shared, next state = Shared-Dirty; otherwise next state = Dirty.Write old line to memory. Issue bus read. If shared, next state = Shared-clean; otherwise next state = Valid-Exclusive.Write old line to memory. Issue bus write miss. Write data to cache. If shared, issue bus write, next state = Shared-Dirty; otherwise next state = Dirty.
DirtySupply data to processor. Next state = Dirty.Write, no delay. Next state = Dirty.Write old line to memory. Issue bus read. If shared, next state = Shared-Clean; otherwise next state = Valid-Exclusive.Write old line to memory. Issue bus write miss. Write data to cache. If shared, issue bus write, next state = Shared-Dirty; otherwise next state = Dirty.
ai.e., if any other cache has the data.
bThis updates all other caches sharing it.

 
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