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The schemes we consider are: |
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Write-Through No Write Allocate (WTNWA) |
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Copy Back Write Allocate (CBWA) |
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Write-Through with a Write Assembly Cache (WAC) |
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Write-Through with CBWA Secondary Cache (WTWSC) |
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The secondary cache is assumed to be CBWA and has a fixed line size of 128 bytes. The sizes of the secondary cache vary across different feature sizes from a minimum of 256KB to 2MB in order to maintain a reasonable size ratio between the level-1 cache and the secondary cache. The first-level cache associated with the secondary cache is WTNWA. |
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(IF/cycle) * secondary cache.MR+(DF + DS)/I * (1 + W)*(secondary cache.MR). |
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Line accesses/cycle * Tline(128B). |
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(Total bus time/cycle)/cycle time. |
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The difference between CBWA and WTNWA is in the write traffic generated. The write-through scheme generates a word write with every processor write request, and the CB scheme generates line writes to write dirty replaced lines back to memory. |
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The basic question is which scheme generates more memory references, and this question is answered quantitatively later. We calculate the total offered occupancy for the data traffic and present the data in the analysis section. |
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Bus saturation occurs when the offered occupancy of the bus is greater than one. Occupancy is defined as the ratio between the traffic that is offered by the CPU (Offered Traffic) and the maximum traffic that can be handled by the memory bus (Achieved Traffic). A rule of thumb for the bus designer is to keep the occupancy of the bus below 0.5. The intuitive reasoning is probabilistic. Since there are different reference streams (data read, data write, instruction read), it is possible for these to conflict with each other, resulting in CPU stalls in certain cases. The quantitative analysis of this involves the references per cycle of the different streams, the bus time of each reference, the traffic filtering effect of caches, and the buffering effect of write buffers. |
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When occupancy is < 1, a probabilistic model can be used to derive the average wait time due to contention. This contention time is added to memory access time and results in higher CPI. When occupancy is > 1, the processor has to slow down to match the bandwidth of the bus, since achieved occupancy can never exceed one. |
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From the preceding relations, it is quite obvious that below a certain miss rate, the write-through traffic dominates all traffic to memory. Write-through |
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