< previous page	page_673	next page >
Page 673 Table 10.5 Branch excess instruction fetch summary. (a) Reduced-Scale Processor Excess When Branch type(assumed path) Taken Not Taken Unconditional 1 Conditional(in-line) 1 0 Conditional(target) 1 0 (b) Super-Pipelined Processor Excess When Branch type(assumed path) Taken Not Taken Unconditional 2 Conditional(in-line) 4 0 Conditional(target) 2 0 ddependency i, and this is weighted by the probability (pdependency i) that there is a dependency at that distance. For the reduced-scale processor, there is only one case that has a penaltya load instruction followed by an ALU operation instruction. In this case, the above equation reduces trivially as: PLD/EX = p0´ 1 = p0 = 0.403, which gives a penalty of 0.403 cycles after weighting. Note that instruction i1 is the load instruction and instruction i2 is the ALU operation instruction. For the super-pipelined processor, there are a number of cases that have nonzero penalties. Consider the same case as before; in the super-pipelined processor, this sequence of instructions has a delay of one half-cycle, corresponding to three instructions, all of which are issued on the half-cycle. In this case, the same equation now reduces to: which gives a penalty of 0.770 cycles. Note that ddependency i (delay penalty) is in terms of half-cycle instead of one-cycle incrementsthis is an artifact of using half-cycle instruction issue in the super-pipelined processor. The results of weighting the penalties based on distance functions are shown in Table 10.6, in the column ''Weighted Delay." To computer branch delays, we have to consider two caseswhether the in-line or target path is the assumed path. To do this, we can calculate the break-even probability of branches that actually go to the target instruction path, and then make our selection of guessed path appropriately. The break-even point for predicting the branch path is found using the equation:
< previous page	page_673	next page >