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8.16 Evaluating Interconnect Networks |
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In recent years, there have been a number of important analyses on the comparative merits of various network configurations [226, 151, 172]. We report on two important developments here. |
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1. Direct networks are preferred over indirect networks, insofar as communication affinity or locality of interconnections can be established for a particular program. Indirect networks necessarily have a uniform interconnect time between nodes. This inability to preferentially site nodes with higher than average communications proves to be a limitation for dynamic and, indeed, all types of indirect networks. Since dynamic networks are generally more expensive than static networks, this is another reason for a preference for static direct network configurations. |
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2. Network topologies must be mapped onto a plane (certainly they must be contained or implemented within three dimensions). Because of this, it is not sufficient to simply count the number of hops required in a high dimensional network to establish a connection, but rather it is more important to look at the length of wire or the delay in transiting wire when that network is mapped onto two dimensions. When one analyzes networks based upon their maximum wire cross section, networks of low dimensionality are preferred. Thus, a two-dimensional mesh can produce significantly less message delay than a higher-order cubic static network. |
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Both of these results have generally pushed machine designers to develop interconnection networks of low dimensionality, statically configured. |
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8.16.1 Direct Static vs. Indirect Dynamic |
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In this section, we present the results and largely follow the analyses performed by Agarwal in his work on network performance [6]. |
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Assume we have a dynamic indirect network made up of k ´ k switches with wormhole routing. Let us assume this network has n stages and channel width w with message length l. In the indirect network, we assume that the header network path address is transmitted in one cycle just before the message leaves the node (i.e., there is only one cycle of header overhead to set up the interconnect); see Figure 8.55. |
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Assuming the switches have unit delay (Tch = one cycle), the total time for a message to transit the network without contention is: |
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For all our subsequent analysis we assume that  so |
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