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Figure 8.24
Cache state transitions for Dragon cache coherency protocol. (Also see
Appendix F.) |
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the previous state. Any cache with a Read Private or Shared Clean copy asserts the SharedLine and changes the copy to the Shared Clean state. The requesting line is then loaded in the Shared Clean state. However, if the line is supplied by memory (no other cache is sharing it), then the state of the cache line is set as Read Private. |
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The write miss case is similar. Upon loading the line, if the line is forwarded from the other caches, the requesting cache sets the state of the line of Shared Dirty and broadcasts the updates on the bus. All other caches with a copy of this line set the state to Shared Clean. If no other cache has a copy, the requesting cache makes the update locally without having to broadcast and the state is set to Private Dirty. |
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For a write hit, if the line is already Private Dirty or Read Private, the write can proceed immediately without the need for broadcasting. For the |
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