|
|
|
|
|
|
|
Figure 8.23
Cache state transitions for Firefly cache coherency protocol. (Also see
Appendix F.) *Read Private is also referred to as Valid Exclusive. |
|
|
|
|
|
|
|
|
change their state to Read Shared. However if the supplier is memory, the requesting cache sets the cache state to Read Private and becomes the owner. On write miss, the line is forwarded from memory or another cache and is updated and set to the Private Dirty state. All other caches invalidate their copies. Note that the Illinois approach only allows a single writer; a dirty cache line is present in only one cache. |
|
|
|
|
|
|
|
|
For a write hit, if the requesting cache is the owner (cache state either Private Dirty or Read Private), the update proceeds without delay. If the line is shared by other caches (Read Shared), the update to the cache line by the requesting cache can only proceed after an invalidate signal is sent on the bus (for other caches to invalidate their copies). The state of the updated cache line is Private Dirty. |
|
|
|
|
|
