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Figure 8.20
Cache state transitions for Write-invalidate cache coherency
protocol. (Also see Appendix F.) |
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Similarly, for a write miss, the block comes directly from the owner (memory or other caches). All other caches with copies of the line invalidate their lines. The requesting cache sets the state of the cache line to Private Dirty and becomes the owner. |
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For a write hit, the requesting cache invalidates all other copies of the cache line and makes the write updates. The new state of the line is set to Private Dirty, regardless of the original state of the line. Note that if the line is already Private Dirty, there is no necessity for invalidation as it is only a copy of the cache line; therefore, the writing can proceed locally without waiting for invalidation. |
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Illinois The Illinois model [225] has four states: Invalid, Read Private (also called valid exclusive), Read Shared, and Private Dirty (also called modified). A cache line which is owned by any cache is either in the Read Private or |
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