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Figure 8.19
Snoopy protocols. (a) A shared bus multiprocessor. (b) Update and
invalidate snoopy protocols. |
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8.9 Shared-Bus Multiprocessors |
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Possibly the most widely studied and most commonly used type of shared memory multiprocessor is the shared bus-shared memory multiprocessor. Consistency must be insured by a protocol which forces the respective processor caches to have a coherent picture of memory for any synchronized code passage. Since all processors share a bus, they can see all transactions. This ensures consistency by broadcasting the transaction. Bus-based protocols are also called snoopy protocols. Each protocol requires a different amount of bus and memory bandwidth and control complexity in managing coherence traffic. Our discussion of these protocols follows the work of Archibald and Baer [21]. There are two basic approaches to snoopy protocol consistency: invalidate and update (Figure 8.19a and b). Protocols assume that all of the processors are aware of, and receive, all bus transactions (they snoop on the bus). There are four well-known variations on the invalidate strategy. These are called: |
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1. Write-invalidate [107]. |
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The alternative protocols are called update protocols. If a write occurs to a line contained in any processor's cache, the write updates any cache that contains that line as well as memory. The two best-known approaches to update protocols are the Firefly [21] and the Dragon [191] approaches. We discuss all these protocols in this section. |
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Snoopy protocols can be categorized not only by whether they invalidate or update shared data lines in remote caches, but also by the source of the new data for a cache line. The data may be provided either by the main |
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